Description
Translates up to two architectural source registers into, committed, physical names.
5-bit Physical Names
4-bit Architectural Registers
Related Schematics
15 bit 5hz multiplier
It's a 15 bit 5 hz combinational multiplier
redstone
logic
computational
+2 more
Jul 31, 2024
8 bit 5hz torchless divider
Pipelineable 5hz 8 bit divider
redstone
logic
computational
+2 more
Nov 29, 2024
Cerebrum-0.4 -- CPU
Cerebrum-0.4, PICOlo_1109's CPUISA: https://docs.google.com/spreadsheets/d/1y0ApeDLECaKg-eRCr1qtvhsx0OteVB7QY5UVcZzkjQQ/edit?gid=0#gid=0NOT FINISHED
redstone
logic
computational
+1 more
Apr 21, 2025
8b vertical decoder
Generated by https://github.com/ZpippoZ/minecraft-vertical-decoder-generator
redstone
logic
computational
+2 more
Aug 22, 2024
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