Description
Checks for RAW dependencies between source and destination operands. Each entry holds allows for up to two source operands and one destination operands, with disables available for fine operand control.
5-bit Operands
5 entries
3op, 2op, 1op compatible
(Not a standalone unit, part of issue logic)
Related Schematics

A CPU for testing
A 8-bit CPU for testing with ALU, Registers, CU, PC, ROM, 0.158Hz CPU

8 bit barrel shifter version A
3 ticks, excluding input/output busleft shift, right shift, arithmetic right shift, rotate. blue: data input, inverted, 15ss required purple: shift amount input, normal, 15ss required.keep in mind that doing a right shift by X is the same as doing a left shift by -X. please input the 2s complement if you want right shifts. yellow: output, normal, low output red: - disable left shift, use when only doing right shift- disable right shift, use when only doing left shift- disable barrelshifter- disable sign extend, for use with arithmetic right shift