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Bycl

Oct 22, 2024 Public
By:
Minecraft
Redstone Logic Computational
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Description

A 32-bit RISC-V processor in Minecraft by StackDoubleFlow.

Related Schematics

JTechGaming
JTechGaming
Hex for-loop 2-wide version

Hex for-loop 2-wide version

Outputs once for every signal strength inputted. So if a signal strength of 7 is inputted, the output will flash 7 times.It has a few nice configuration options:- You can change the pulse duration of the output by increasing the delay on the repeater going into the comparator. Keep in mind that the delay on the repeater next to it needs to be equal to the delay of the repeater going into the comparator.- You can also change the delay between pulses by expanding the pulse extenderI also made a version that is one block longer and doesn't use a redstone lamp, but it is 3-wide instead of 2-wide. You can find that on my account page as well.

Jul 14, 2025
View Hex for-loop 2-wide version
Vaaaaampi
Vaaaaampi
Simple 16*8bits reg

Simple 16*8bits reg

Inspired on mattbatwings' design

Oct 20, 2024
View Simple 16*8bits reg
Nano_
Nano_
awale

awale

The game of awale

redstone logic
Aug 01, 2024
View awale
Wueffi
Wueffi
February 2025 Competition Evaluator

February 2025 Competition Evaluator

Evaluator for the February 2025 ORE Competition

redstone logic computational +3 more
Feb 12, 2025
View February 2025 Competition Evaluator

Details

ID:
8k81sf
Created:
11 months ago
Format:

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