Logo

Sign In

Or continue with
Logo

Register

To register, connect to the auth server:
Once connected, type the following command:
Or use your Microsoft account to login without registering.

Home / Schematics / Bycl

Bycl

Oct 22, 2024 • Public
Your browser does not support the HTML5 canvas tag.
By:
StackDoubleFlow
Tags:
Minecraft
Width
Depth
Height
Version
Redstone
Logic
Computational
Bit width
data format
input orientation
throughput
latency
mchprs optimised

Description

A 32-bit RISC-V processor in Minecraft by StackDoubleFlow.

Related Schematics

zPippo_
zPippo_
6b vertical decoder

6b vertical decoder

Generated by https://github.com/ZpippoZ/minecraft-vertical-decoder-generator

redstone logic computational +2 more
Aug 22, 2024
View 6b vertical decoder
TosinV1
TosinV1
1ss 3t CCA

1ss 3t CCA

An 8-Bit 3 tick CCA (with Cout and Cin) Features: 1 signal strength minimum, soft input (not hard-powered) and doesn't require both input to have the same signal strength. This tech allows to chain adders together without the need of a repeater in between, which is helpful for circuits like Multiplier. Altough this current layout is hard to connect to each other. This adder is just a proof of concept. Theory and Design by Tosin, made in April 21st, 2024

redstone logic computational +1 more
Sep 01, 2024
View 1ss 3t CCA
Nano_
Nano_
test

test

test

Jan 29, 2025
View test
dfgch
dfgch
Horizontal cache

Horizontal cache

Horizontal cache

redstone logic memory
Apr 08, 2025
View Horizontal cache

Download Options

Download Schematic File
In-game command:
/schematio download 8k81sf

Schematic Details

  • Created: Oct 22, 2024
  • Visibility: Public
  • Type: N/A
  • ID: 8k81sf

Share